Restricted Research - Award List, Note/Discussion Page

Fiscal Year: 2021

212  University of North Texas  (84508)

Principal Investigator: Zhao,Hui

Total Amount of Contract, Award, or Gift (Annual before 2011): $ 172,573

Exceeds $250,000 (Is it flagged?): No

Start and End Dates: - 6/30/23

Restricted Research: YES

Academic Discipline: Computer Science & Engineering

Department, Center, School, or Institute: College of Engineering

Title of Contract, Award, or Gift: Collaborative Research: SHF: Small: Tangram: Scaling into the Exascale Era with Reconfigurable Aggregated "Virtual Chips"

Name of Granting or Contracting Agency/Entity: National Science Foundation

Program Title: N/A
CFDA Linked: Computer and Information Science and Engineering


Computers have revolutionized the way we live, and without question, they still will. In the past decades, the advances in VLSI enable us to integrate more transistors into a single chip, resulting in an exponential growth of performance. Unfortunately, this exponential growth has been drastically slowed down due to the limitations in technology scaling. Chiplet-based Systems-in-a-Package offers a promising solution for heterogeneous system integration. Using this technique, small dies (called chiplets) for CPUs, GPUs and FPGAs can be integrated inside one package. Chiplets can resolve the scaling problem of monolithic chips and allow each individual functional block to be manufactured with specific materials and processes. They can also reduce the overall cost by improving the wafer yield. However, chiplets do not magically re-enable the sort of CPU scaling we used to see, and they do not automatically offer better performance. Inter-chiplet communication becomes system bottleneck constraining optimal resource management and effective sharing. The goal of this proposed research is to enable the creation of "virtual chips" from heterogeneous aggregated chiplets, so that the SoC can not only reap the performance benefit of a monolithic chip but also break the scalability bottleneck. Keywords: many-core; SoC; architecture; heterogeneous multi-processor; chiplet; NoC

Discussion: No discussion notes


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